iCD's Design Integrity

When it comes to high-speed design, the name of the game is understanding and controlling impedance.

At first glance, you may wonder why ICD put together software that seems to address 2 nearly unrelated areas. The stack-up planner addresses the layers. The PDN planner addresses the use of capacitors. What gives?

When we look at the high-speed design, we are dealing with the effect of impedance on the traces and the power provided to the board. The trace impedances are heavily influenced by the layer stack up.

On the power planes, we also deal with impedances. Any noise that makes its way onto the Power Distribution Network (PDN) (a.k.a the power planes) needs to be given a low impedance path to the ground plane, regardless of the noises' frequencies. Thus the need to determine which values of capacitors are needed, what kind, and how many. The PDN Planner provides over 6500 capacitors in the library. More will be added as they become available. The user can add capacitors to the library as well.

The iCD stackup planner provides accurate impedance information through its built-in field solver. By using the information in the stack-up planner, the PDN planner can, in turn, provide accurate information for all noise frequencies of concern. With the iCD stack up the planner, the user can access a library of over 23,230 materials (core, prepreg, and solder mask) up to 100 GHz.

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Regarding The Price of The PowerStack Suite

When one considers the iCD PowerStack Suite cost versus the engineering labor cost to manually develop a complex stack-up solution, the Return On Investment (ROI) is worth further consideration.

Consider the following calculations. The ICD PowerStack Suite is $4,995. According to the site https://www.sokanu.com/careers/electrical-engineer/salary as of September 2016, the average salary of a senior engineer is ~$93,000/year. $4,995 equates to a little less than 3 weeks of engineering labor. Granted, one who does PCB stackups all the time or a well-seasoned engineer could take less time. However, few engineers are experts in layer stack-ups, and more so, few engineers who are trained in such matters may only use this knowledge two or three times a year. In engineering, the old saying “use it or lose it” rings true.

A layer stack-up for complex designs is not trivial. The days of simply using FR-4 for the dielectric are over. Anyone putting together a complex board has to do some research into the various materials. Unlike FR-4, several different materials must be used, each with its advantages and disadvantages. The research includes downloading the spec sheets, reading them thoroughly, making decisions, and verifying the proposed stack-up with the fabricator. That alone can take a couple of days on a complex board.

Calculations for impedance, trace spacing, and trace width are not trivial. They require field solvers for accuracy. Even if the stack-up is manufacturable, failure to get the calculations right will be very costly. Scrapped boards and the labor costs for redesign due to erroneous impedance and trace values are tens of thousands of dollars.

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