Designing a Stackup for High-Speed Design

The physical makeup of the board itself plays the dominant role in establishing impedances and signal propagation speeds. It can no longer be an afterthought if one wishes to assure signal integrity. Though your fabricator is happy to provide you with a stackup, you need to know what you want before approaching them.
This webinar will guide you through the process of verifying your stackup. The webinar will cover:

• Material section
  

• Differential pair width/pitch
  

• Optimal via geometry
  

We will use this information to perform a time-domain verification using the Simbeor Electromagnetic Analysis Tool. Attending this webinar will give you the tools and knowledge you need to confidently design your stackup and interconnect geometry for first-pass success.

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What defines high speed in electronic design?

At Nine Dot Connects, we often ask the following question: "What's the frequency in which a design is considered high speed?" Would it surprise you that a 10 MHz design that could be wire wrapped or placed on a protoboard could constitute high speed? The fact is, frequency is only a part of the story.

The bigger question is, "What factors qualify the circuit as high speed?" Issues such as electromagnetic interference (EMI), cross talk, receiver noise floor, and signal propagation all come into play. It is not just about avoiding or mitigating these issues; it's about optimizing the communication path.

We will address what qualifies a circuit as being high-speed. Sean Kelly, who has recently provided several introductory webinars on high-speed in the past, will be presenting. We encourage you to take a look at these prior recordings in addition to joining us for our live webinar on our website.

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What Drives a High-Speed Signal: Voltage or Current?

In the January 2014 webinar High-Speed Design Rules, we showed an experiment whose results seemed to defy the rule of thumb that states electricity takes the path of least resistance.

Connect a power supply to a metal table and run the power supply's wire output parallel to the table.
After a 2m run, bend the wire 90 degrees and run it for 1.4m before bending it again onto the table. Now power up the circuit and measure the current density. One would expect the current return path to run the hypotenuse of the circuit triangle. Yet, this does not happen!


So what's the deal? Is this a current or voltage phenomenon? It is a field phenomenon. The key to controlling all forms of interference, including EMI, is to control and contain the electric and magnetic fields in our printed circuit boards. Many of the common PCB design practices used by designers allow fields to spread, creating the issues we often encounter.

This month, our webinar, PC Board Design to Contain and Control Fields, will be presented by Rick Hartley. Rick has decades of high-speed design experience and has led the way in many bespoke practices today.

This 1-hour webinar will help you understand the best methods to minimize interference. Topics covered:

• Location of the Energy in a circuit
  

• What causes Energy to spread
  

• Transmission Lines and Return Current Paths
  

• Proper and Improper use of Planes in a PC board
  

• Trace Routing to Contain Fields
  

• PCB Layer Stack-ups that cause problems
  

• PCB Layer Stack-ups that eliminate problems
  

Q&A from Webinar

Recommended Books

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Double Data Rate (DDR3) Shouldn't be Double Trouble - Part 1

There's a lot of talk about the 3rd generation of Double Data Rate memory known as DDR3. We at Nine Dot Connects have laid out several DDR3 boards in the past three months. There is quite a bit of detail about DDR3 design and layout; unfortunately, there is also a lot of misinformation. We have waded through and analyzed the literature. We wish to share our findings and understanding with you.

Our two-part series on this topic will first cover critical concepts necessary for proper signal integrity and general DDR3 design. Topics to be covered this month are:

• Brief history of the DDR concept
  

• Comparison between the different generations of DDR
  

• The signaling and timing requirements for DDR3
  

• Understanding match length versus match delay
  

• Compensating for typical routing delay
  

• Using the iCD Stackup Planner to assist in the delay-matching calculation
  

In part 2, we will build upon this foundation by demonstrating practical aspects of DDR3 layout techniques.

Q&A from Webinar

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Practical DDR3 - Part 2

In part 1 of our DDR3 webinar, we established some key points to consider when handling the timing issues of DDR3. In part 2, we will introduce the following copper-related aspects of DDR3:

• Serpentines
  

            - Why they are needed
            - When to use them
            - Proper methods
            - Issues that occur when not done correctly

• Signal Group and swapping
  

• Pin delays and swapping
  

• On-Die-Termination (ODT)
  

            - What is it
            - Why it is important

• Vias
  

We will demonstrate these concepts and address rules, schematic issues, length matching, and xSignals in Altium Designer. Please note that many of these concepts apply to other EDA tools.

Q&A from Webinar

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Practical Aspects of Signal Integrity - Part 1

"There are two kinds of engineers: those who have signal integrity problems and those that will." - Eric Bogatin


At Nine Dot Connects, we will be the first to admit that Signal Integrity (SI) analysis has not been one of our primary concerns. We believed that following "best practices" would be sufficient for all of our high-speed design needs for years. And it also seemed more cost-effective to do a respin or two rather than spend the money to purchase and learn advanced SI tools.

However, times change, and reality has reared its ugly head. Faster signal transitions, tighter layouts, lower voltage levels, costly high-density parts, and shorter production cycles are all conspiring to make SI analysis an absolute necessity for a successful product.

Lifecycle Insights (September 2018) found that the average number of respins was 2.9, and the average cost of a respin was an incredible $28,482.

In response, we have a webinar to present how SI analysis can be applied to real-world design examples. Tom Cassidy, who has years of experience doing high-speed design and layout, will present a series of common layout paradigms and how SI can be used to identify potential problems and provide solutions. The webinar will culminate with a finished DDR3 design, showing how SI analysis can help ensure a working layout the first time.

Although this webinar will use a board designed in Altium and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

Q&A from Webinar

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Practical Aspects of Signal Integrity - Part 2

"There are two kinds of engineers: those who have signal integrity?problems and those that will." - Eric Bogatin


In part one of our webinar on "Practical Aspects of Signal Integrity," Tom Cassidy provided the basic design concepts to consider when laying out a board for high-speed signals to ensure the signal's integrity. If you missed it, we encourage you to watch the recording of this webinar. The concepts presented build upon each other.

Watch Part 1

In part two, Tom will be presenting on several design use cases, including:

• Reference Planes
  

• Stripline vs. Microstrip
  

• Differential Pairs
  

• Termination
  

• Crosstalk
  

• Fly-by vs. T-Branch
  

• Complete DDR3 layout
  

Although this webinar will use a board designed in Altium Designer and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

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Practical Aspects of Signal Integrity - Part 3

"There are two kinds of engineers: those who have signal integrity problems and those that will." - Eric Bogatin


In parts 1 and 2 of our webinar on "Practical Aspects of Signal Integrity," Tom Cassidy provided the basic design concepts to consider when laying out a board for high-speed signals to ensure the signal's integrity. If you missed one or both, we encourage you to watch the recording of these webinars. The concepts presented build upon each other.

Watch Part 1

Watch Part 2

In Part 3 of this webinar series, Tom will present the simulation and analysis of a functional FPGA-based DDR3 memory design. He will also examine some common layout paradigms inherent to DDR3 and explore their signal integrity implications.

• Xilinx Zynq FPGA and Micron DDR3 Memory
  

• "Power-aware" Simulation and Analysis
  

• JEDEC Compliance Reports
  

• Signal Termination
  

• Differential Pair Routing Concerns
  

• Alternate Routing Paradigms
  

Although this webinar will use a board designed in Altium Designer and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

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Practical Aspects of Serial Communications - Part 4

Serial communication is a lot like the display of cascading dominoes. The cascade (energy propagating from one end to the other) relies upon each domino falling in the right direction with enough momentum to cause the next domino to fall. Serial communication is not much different when propagating an energy wave, which we call a "signal," along a trace. But unlike cascading dominoes, which make for interesting Rube Goldberg machines, we should not have to hold our breath and hope for the best regarding the signal integrity of our serial communication lines on a PCB.

Part 4 of the Nine Dot Connects "Practical Aspects" webinar series will focus on serial communications. We will cover several communication paradigms, including SPI, PCIe, and USB3.0, using Cadence's Sigrity toolset to demonstrate these concepts. Additionally, this webinar will explore how high-speed serial bus design aspects cross over into the advanced parallel design world.

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The accidental antenna and how to make one

There are antennas, and then there are accidental antennas. Accidental antennas are the noisemakers of your PCB design. They are created when the board's copper takes on a role beyond its job of connecting point A to point B.

If an accidental antenna did not wreak havoc on the test bench or with the initial prototype, their presence often would be felt during FCC testing when the project is already a dollar short and a day late.

This webinar will examine accidental antennas and provide some guidance as to how to avoid creating them. The three objectives of this webinar:

• Does a properly created microstrip behave as an antenna?
  

• What changes can be made to increase/decrease such behavior?
  

• What makes a good shield?
  

As much as we would like to boil this down to simple "rules of thumb," some concepts should first be reviewed. We encourage you to review our recent publicly released videos that will provide additional information that you may find beneficial:


Transmission Line AC Impedance    

Watch the Video

What is 50 Ohm Impedance?         

Watch the Video

Q&A from Webinar

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High-Speed Topic: The stuff that makes up signal integrity - AC Impedance

We introduced the concept of impedance as it relates to both cables and printed circuit boards. However, that conversation was kept concerning Direct Current (DC) to establish the fundamental concept of impedance. If you missed this webinar or would like to refresh yourself on the topic, please check out the link and request the video recording:

DC Impedance Video

In this video, we will continue to discuss impedance from the AC perspective. This is imperative since high-speed signal integrity entirely relies on knowing the impedance issues and requirements.

We will compare AC and DC impedances during this video, take a closer look at the composition of a square wave, delve into the S-parameters (scatter parameters), S12 for isolation, and S21 for insertion loss, and then see how these aspects apply to the PCB.

Sean Kelly, one of the senior RF/high-speed engineers here at Nine Dot Connects, will be presenting.

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High-Speed Topic: What is meant by a 50-ohm impedance?

In our past videos, we have discussed characteristic impedance related to the layer stack-up of the PCB. However, we have yet to address the notion of impedance itself. Impedance has always been part of the signal traces on a PCB but is not necessarily a concern. With high-speed designs becoming more prevalent and significantly faster-rising edge times now common on all digital components (even the classic 7400 logic gate series), understanding impedance is becoming a critical concern. Many of the intermittent failures one may experience can be traced back to impedance issues.

In this deep dive, the focus will be on the fundamentals of impedance:

• Review the classic approach of the voltage/current relationship and explain why the inductance to capacitance relationship creates the same kind of relationship, hence the term 'characteristic impedance.'
  

• Discuss the three functions of impedance: power transfer, reflections, and radiation. Understanding and managing these three critical functions can help avoid attenuation, signal distortion, and cross talk.
  

• Review of T-line theory as an infinite transmission line
  

Sean Kelly will give this presentation. Sean has been in the electronics industry for 30 years, with 20 years of experience in PCB design. Also, Sean is an instructor and consultant on topics such as high-speed design and RF.

Q&A's from Webinar

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High-Speed Design Series - RF Part 1

Though Nine Dot Connects is a Value Added Reseller (VAR) of electrical engineering design tools, we have rapidly expanded our capabilities to provide design services in all aspects of the PCB design flow. We have several talented individuals who have mastered PCB design, and their stories and experiences embody the engineering spirit that brought each of us into this industry. But more so, they wish to impart their knowledge to the engineering community on topics many of us wish to tackle and understand.

This August, we will start a 3-part series on High-Speed Design concepts.

Our August webinar will introduce Gary Gaddie, a +30-year veteran of the PCB industry. Gary has worked in both the military and commercial spaces. He is involved with the IPC and is CID++. Gary keeps abreast of the changes and innovations in PCB manufacturing and assembly technologies, allowing him to literally "Design for Manufacturing" (DFM). Gary will be discussing the basics of RF concepts in PCB design.

Topics will cover practical issues including (but not limited to):

• Antenna placement
  

• Waveguides
  

• Via stitching and via spacing
  

• Antipads
  

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High-Speed Design Series - EM/SI Part 2

In August, we started a 3-part series on High-Speed Design concepts. This month, Jeff Condit will focus on noise mitigation in high-speed design. Jeff has over 40 years of experience in many electrical engineering facets such as hardware, software, systems, RF, digital and analog, and work experiences that range from military to commercial and everything in between. His talents extend to the ability to present engineering concepts concisely and logically.

Jeff will address the need for noise mitigation in high-speed PCB designs:

• Identifying unintended antennas and resonators on your board
  

• Brief review of the fundamentals as to why noise comes about
  

• Concerns one must address when laying out digital designs
  

• Transforming impedances without creating reflections
  

• Practices one can use to mitigate noise on the board
  

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High-Speed Design Series - PCB/SI Part 3

In August, we started a 3-part series on High-Speed Design concepts. In part 3 of our series, Jeff Condit will continue discussing noise mitigation in high-speed design. The September webinar focused on the fundamentals necessary to gain an intuitive feel for High-Speed Design.

Jeff will address the need for noise mitigation in high-speed PCB designs:

• Concerns one must address when laying out digital designs
  

• Transforming impedances without creating reflections
  

• Practices one can use to mitigate noise on the board
  

Jeff has over 40 years of experience in many electrical engineering facets such as hardware, software, systems, RF, digital and analog, and work experiences that range from military to commercial and everything in between. His talents extend to the ability to present engineering concepts concisely and logically.

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Enough with high-speed theory already. Give me something real! - Part 1

In the past, we at Nine Dot Connects have presented much theory on high-speed design. That's all well and necessary, but at some point, we need to know how to apply it to a real board.

When we approached our resident expert Sean Kelly on the topic of a webinar that would show practical elements of high-speed design, he returned with a rather robust outline. We concluded that there was no way we could do this in 1 hour!

Starting this February, we will start a 3 part series on the practical application of high-speed design in PCBs. This month we will focus on the PCB behavior, which is just as much of a component as it is a medium for interconnecting components. In this first webinar, we discuss the effects of the PCB on the propagation of the signal.

To note, the second webinar will be dedicated to routing as it relates to high-speed design. Our third webinar will go into detail about the material considerations when putting together a stack-up. Though we have covered stack-ups in prior webinars, this third webinar will show real examples that Sean has used in the past and the rationale behind their configurations and the materials selected.

Q&A's from Webinar

We provide the video recording of the 3-part webinar series.

Watch the Series

Coping with Copper in High Speed Design - Part 2

When we consider the physical aspects of high-speed design, there are 2 key concepts - the proper form of the copper in terms of traces, vias, pours, and the board infrastructure to support it. In our prior webinar, we spent some time looking at the dielectrics and how they influence the signal. If you wish to review these concepts, please click on the link below.

Previous Webinar

In this webinar, we will focus on the traces, but more importantly, the reference planes. In fact, it is tough to create a high-speed design without reference planes. By addressing the reference planes, we can avoid most of the gotchas that plague high-speed designs. And, of course, trace practices will also be addressed.

This will also be interactive to help keep you on your toes. Throughout the webinar, we plan to poll to gauge the audience's understanding and focus on those areas that may need more explanation. Also, our presenter Sean Kelly will be showing examples of good and poor practices.

Q&A's from Webinar

We provide the video recording of the 3-part webinar series.

Watch the Series

The Superstructure PCB - Part 3

It bears repeating in high-speed design. The board's makeup plays a monumental role in impedance calculations and provides the structure necessary for signal integrity issues.

We have presented the need for reference planes and tools such as the iCD Design Integrity in the past. In our last webinar (part 2 of the 3-part Practical High-Speed Design series), we provided key points for routing in a high-speed environment. Now it is time to get the nitty-gritty of the PCB superstructure.

In this webinar, presented by our high-speed expert Sean Kelly, we will focus on the materials beyond the traditional FR-4. We will also look at the impact of the component packages on the signal. We will also present various stack-ups that are optimal for high-speed design.

This is part 3 of the "Practical High-Speed Design" series. You can find information on parts 1 and 2 of the series here.

Part 1

Part 2

You can download the list of questions and answers for this webinar here.

Q&A's from Webinar

We provide the video recording of the 3-part webinar series.

Watch the Series

Mastering the Matching of the Lines - xSignals and Length Tuning

Nine Dot Connects is no stranger to complex high-speed designs with tight timing constraints. While length-matched signals may be aesthetically pleasing, the effort required to obtain the result can be daunting. The concepts include matched single and differential signals, T-branches, daisy-chain (fly-by) routing, and serial terminations. Properly using Length Tuning and xSignals is critical to deal with these issues efficiently.

This webinar will show the functionality of both Length Tuning and xSignals in Altium Designer. Given that we have not covered the creation of differential signals in Altium Designer in prior webinars, a brief primer will be given.

In addition to some tool instruction, Tom Cassidy, our resident expert in DDR3/4 and other high-speed copper configurations, will demonstrate 'real world' uses of both features. Some many tips and tricks that can make the process more efficient.

3 Banks of DDR4s, 3 large FGPAs, and 96 Pairs of 15 Gbps Signals Design
Performed by Nine Dot Connects

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Power Distribution Network & Power Integrity

Though signals tend to focus on impedance issues, the power distribution network (PDN) on the board is just as susceptible to impedance. The PCB layer stack-up is a capacitor all its own, and with the addition of bypass capacitors and inductors on the board, the ability to distribute power to avoid power starvation or to reduce ripple becomes an integral part of the design.

Topics include:

• The power distribution network and how impedances interrupt and starve components of the power they require.
  

• Dive deeper into the impedances caused by capacitors and inductors and, more importantly, how they interact.
  

• How to manage the impedance by a careful selection of capacitors.
  

We will use the iCD PDN Planner tool to see the results as we present them visually.

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