Double Data Rate (DDR3) Shouldn't be Double Trouble - Part 1

There's a lot of talk about the 3rd generation of Double Data Rate memory known as DDR3. We at Nine Dot Connects have laid out several DDR3 boards in the past three months. There is quite a bit of detail about DDR3 design and layout; unfortunately, there is also a lot of misinformation. We have waded through and analyzed the literature. We wish to share our findings and understanding with you.

Our two-part series on this topic will first cover critical concepts necessary for proper signal integrity and general DDR3 design. Topics to be covered this month are:

• Brief history of the DDR concept
  

• Comparison between the different generations of DDR
  

• The signaling and timing requirements for DDR3
  

• Understanding match length versus match delay
  

• Compensating for typical routing delay
  

• Using the iCD Stackup Planner to assist in the delay-matching calculation
  

In part 2, we will build upon this foundation by demonstrating practical aspects of DDR3 layout techniques.

Q&A from Webinar

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Practical DDR3 - Part 2

In part 1 of our DDR3 webinar, we established some key points to consider when handling the timing issues of DDR3. In part 2, we will introduce the following copper-related aspects of DDR3:

• Serpentines
  

            - Why they are needed
            - When to use them
            - Proper methods
            - Issues that occur when not done correctly

• Signal Group and swapping
  

• Pin delays and swapping
  

• On-Die-Termination (ODT)
  

            - What is it
            - Why it is important

• Vias
  

We will demonstrate these concepts and address rules, schematic issues, length matching, and xSignals in Altium Designer. Please note that many of these concepts apply to other EDA tools.

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Mastering the Matching of the Lines - xSignals and Length Tuning

Nine Dot Connects is no stranger to complex high-speed designs with tight timing constraints. While length-matched signals may be aesthetically pleasing, the effort required to obtain the result can be daunting. The concepts include matched single and differential signals, T-branches, daisy-chain (fly-by) routing, and serial terminations. Properly using Length Tuning and xSignals is critical to deal with these issues efficiently.

This webinar will show the functionality of both Length Tuning and xSignals in Altium Designer. Given that we have not covered the creation of differential signals in Altium Designer in prior webinars, a brief primer will be given.

In addition to some tool instruction, Tom Cassidy, our resident expert in DDR3/4 and other high-speed copper configurations, will demonstrate 'real world' uses of both features. Some many tips and tricks that can make the process more efficient.

3 Banks of DDR4s, 3 large FGPAs, and 96 Pairs of 15 Gbps Signals Design
Performed by Nine Dot Connects

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