Practical Aspects of Signal Integrity - Part 1

"There are two kinds of engineers: those who have signal integrity problems and those that will." - Eric Bogatin


At Nine Dot Connects, we will be the first to admit that Signal Integrity (SI) analysis has not been one of our primary concerns. We believed that following "best practices" would be sufficient for all of our high-speed design needs for years. And it also seemed more cost-effective to do a respin or two rather than spend the money to purchase and learn advanced SI tools.

However, times change, and reality has reared its ugly head. Faster signal transitions, tighter layouts, lower voltage levels, costly high-density parts, and shorter production cycles are all conspiring to make SI analysis an absolute necessity for a successful product.

Lifecycle Insights (September 2018) found that the average number of respins was 2.9, and the average cost of a respin was an incredible $28,482.

In response, we have a webinar to present how SI analysis can be applied to real-world design examples. Tom Cassidy, who has years of experience doing high-speed design and layout, will present a series of common layout paradigms and how SI can be used to identify potential problems and provide solutions. The webinar will culminate with a finished DDR3 design, showing how SI analysis can help ensure a working layout the first time.

Although this webinar will use a board designed in Altium and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

Q&A from Webinar

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Practical Aspects of Signal Integrity - Part 3

"There are two kinds of engineers: those who have signal integrity problems and those that will." - Eric Bogatin


In parts 1 and 2 of our webinar on "Practical Aspects of Signal Integrity," Tom Cassidy provided the basic design concepts to consider when laying out a board for high-speed signals to ensure the signal's integrity. If you missed one or both, we encourage you to watch the recording of these webinars. The concepts presented build upon each other.

Watch Part 1

Watch Part 2

In Part 3 of this webinar series, Tom will present the simulation and analysis of a functional FPGA-based DDR3 memory design. He will also examine some common layout paradigms inherent to DDR3 and explore their signal integrity implications.

• Xilinx Zynq FPGA and Micron DDR3 Memory
  

• "Power-aware" Simulation and Analysis
  

• JEDEC Compliance Reports
  

• Signal Termination
  

• Differential Pair Routing Concerns
  

• Alternate Routing Paradigms
  

Although this webinar will use a board designed in Altium Designer and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

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Practical Aspects of Signal Integrity - Part 2

"There are two kinds of engineers: those who have signal integrity?problems and those that will." - Eric Bogatin


In part one of our webinar on "Practical Aspects of Signal Integrity," Tom Cassidy provided the basic design concepts to consider when laying out a board for high-speed signals to ensure the signal's integrity. If you missed it, we encourage you to watch the recording of this webinar. The concepts presented build upon each other.

Watch Part 1

In part two, Tom will be presenting on several design use cases, including:

• Reference Planes
  

• Stripline vs. Microstrip
  

• Differential Pairs
  

• Termination
  

• Crosstalk
  

• Fly-by vs. T-Branch
  

• Complete DDR3 layout
  

Although this webinar will use a board designed in Altium Designer and analyzed in Cadence Sigrity, the concepts apply to any tier-one analysis tool.

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Practical Aspects of Serial Communications - Part 4

Serial communication is a lot like the display of cascading dominoes. The cascade (energy propagating from one end to the other) relies upon each domino falling in the right direction with enough momentum to cause the next domino to fall. Serial communication is not much different when propagating an energy wave, which we call a "signal," along a trace. But unlike cascading dominoes, which make for interesting Rube Goldberg machines, we should not have to hold our breath and hope for the best regarding the signal integrity of our serial communication lines on a PCB.

Part 4 of the Nine Dot Connects "Practical Aspects" webinar series will focus on serial communications. We will cover several communication paradigms, including SPI, PCIe, and USB3.0, using Cadence's Sigrity toolset to demonstrate these concepts. Additionally, this webinar will explore how high-speed serial bus design aspects cross over into the advanced parallel design world.

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